Evaluation of FPGA to PC feedback loop

Pawel Linczuk; Wojciech M. Zabolotny; Andrzej Wojenski; Rafal D. Krawczyk; Krzysztof T. Pozniak; Maryna Chernyshova; Tomasz Czarski; Michal Gaska; Grzegorz Kasprowicz; Ewa Kowalska-Strzeciwilk; Karol Malinowski

doi:10.1117/12.2280947

7 August 2017 Evaluation of FPGA to PC feedback loop

Pawel Linczuk, Wojciech M. Zabolotny, Andrzej Wojenski, Rafal D. Krawczyk, Krzysztof T. Pozniak, Maryna Chernyshova, Tomasz Czarski, Michal Gaska, Grzegorz Kasprowicz, Ewa Kowalska-Strzeciwilk, Karol Malinowski

Author Affiliations +

Proceedings Volume 10445, Photonics Applications in Astronomy, Communications, Industry, and High Energy Physics Experiments 2017; 104454B (2017) https://doi.org/10.1117/12.2280947
Event: Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2017, 2017, Wilga, Poland

Abstract

The paper presents the evaluation study of the performance of the data transmission subsystem which can be used in High Energy Physics (HEP) and other High-Performance Computing (HPC) systems. The test environment consisted of Xilinx Artix-7 FPGA and server-grade PC connected via the PCIe 4xGen2 bus. The DMA engine was based on the Xilinx DMA for PCI Express Subsystem¹ controlled by the modified Xilinx XDMA kernel driver.² The research is focused on the influence of the system configuration on achievable throughput and latency of data transfer.

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Pawel Linczuk, Wojciech M. Zabolotny, Andrzej Wojenski, Rafal D. Krawczyk, Krzysztof T. Pozniak, Maryna Chernyshova, Tomasz Czarski, Michal Gaska, Grzegorz Kasprowicz, Ewa Kowalska-Strzeciwilk, and Karol Malinowski "Evaluation of FPGA to PC feedback loop", Proc. SPIE 10445, Photonics Applications in Astronomy, Communications, Industry, and High Energy Physics Experiments 2017, 104454B (7 August 2017); https://doi.org/10.1117/12.2280947

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