CCD focal-plane real-time image processor

Sayed I. Eid; Eric R. Fossum

doi:10.1117/12.24219

1 September 1990 CCD focal-plane real-time image processor

Sayed I. Eid, Eric R. Fossum

Proceedings Volume 1360, Visual Communications and Image Processing '90: Fifth in a Series; (1990) https://doi.org/10.1117/12.24219
Event: Visual Communications and Image Processing '90, 1990, Lausanne, Switzerland

Abstract

A focal-plane-array chip designed for real-time, general-purpose, image preprocessing is reported. A 48 X 48 pixel detector array and a 24 X 24 processing element processor array are monolithically integrated on the chip. The analog, charge-coupled device-based VLSI chip operates in the charge domain and has sensing, storing, and computing capabilities. The chip was fabricated with a double-poly, double-metal process in a commercial CCD foundry. The simulation of an edge detection algorithm implemented by the chip is presented. An overview of the chip performance is described as well.

Citation Download Citation

Sayed I. Eid and Eric R. Fossum "CCD focal-plane real-time image processor", Proc. SPIE 1360, Visual Communications and Image Processing '90: Fifth in a Series, (1 September 1990); https://doi.org/10.1117/12.24219

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