High-speed hardware architecture for high-definition videotex system

Mitsuru Maruyama; Hiroaki Sakamoto; Yutaka Ishibashi; Kazutoshi Nishimura

doi:10.1117/12.50267

1 November 1991 High-speed hardware architecture for high-definition videotex system

Mitsuru Maruyama, Hiroaki Sakamoto, Yutaka Ishibashi, Kazutoshi Nishimura

Proceedings Volume 1605, Visual Communications and Image Processing '91: Visual Communication; (1991) https://doi.org/10.1117/12.50267
Event: Visual Communications, '91, 1991, Boston, MA, United States

Abstract

An experimental high-definition videotex system for broadband ISDN has been developed, and this paper introduces high-speed hardware architecture for this system. Key technologies required are highspeed protocol processing, high-speed data transfer, and high-speed picture readout. High-speed protocol processing — using a newly developed virtual memory copy, contents rearrangement memory, two-bus architecture, and simultaneous editing and analyzing — allows a requested 6-MB picture to be displayed within 3 seconds.

Citation Download Citation

Mitsuru Maruyama, Hiroaki Sakamoto, Yutaka Ishibashi, and Kazutoshi Nishimura "High-speed hardware architecture for high-definition videotex system", Proc. SPIE 1605, Visual Communications and Image Processing '91: Visual Communication, (1 November 1991); https://doi.org/10.1117/12.50267

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