Multimedia RISC core for efficient bitstream parsing and VLD

Mladen Berekovic; Gerhard Meyer; Yong Guo; Peter Pirsch

doi:10.1117/12.304665

26 March 1998 Multimedia RISC core for efficient bitstream parsing and VLD

Mladen Berekovic, Gerhard Meyer, Yong Guo, Peter Pirsch

Proceedings Volume 3311, Multimedia Hardware Architectures 1998; (1998) https://doi.org/10.1117/12.304665
Event: Photonics West '98 Electronic Imaging, 1998, San Jose, CA, United States

Abstract

Demand for highly flexible and fast implementations for bitstream parsing and variable-length-decoding (VLD) arises, if applications are targeted that shall support either MPEG- 4 or multiple standards like MPEG-2, H.263 or Dolby AC3. The paper shows that especially today's multimedia oriented RISC processors incorporating multiple parallel arithmetic units are slowed down by these kind of bit-level operations. Therefore, a new architecture is proposed, that adds function specific blocks into the data path of a RISC processor, that are highly adapted to the processing of variable-length coded bitstream data. The increased functional complexity of basic instructions results in a significant speedup over software implementations on standard RISC processors. Two typical functions, that are frequently used in bitstream parsing, ShowBits and GetBits, are executed in a single clock-cycle with a 64 bit rotator circuit. Constant input-rate VLD of one, two or four bits per clock-cycle can be implemented using internal RAM. Look- up-tables can be used for word-parallel decoding and VLC. Optionally memory entries can be saved using content addressable memories in addition to a data RAM. The proposed architecture has been implemented as a functional extension to an existing RISC core with additional 9k gates of logic, 8k RAM and an interface to a CAM. Synthesis result show an estimate of 160 MHz achievable clock frequency using a 0.35 (mu) technology. The resulting performance is sufficient for MPEG-2 HDTV or MPEG-4 applications.

Citation Download Citation

Mladen Berekovic, Gerhard Meyer, Yong Guo, and Peter Pirsch "Multimedia RISC core for efficient bitstream parsing and VLD", Proc. SPIE 3311, Multimedia Hardware Architectures 1998, (26 March 1998); https://doi.org/10.1117/12.304665

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