Low-cost reconfigurable DSP-based parallel image processing computer

Ciaron W. Murphy; David Mark Harvey; Laurence J. Nicolson

doi:10.1117/12.327028

8 October 1998 Low-cost reconfigurable DSP-based parallel image processing computer

Ciaron W. Murphy, David Mark Harvey, Laurence J. Nicolson

Proceedings Volume 3526, Configurable Computing: Technology and Applications; (1998) https://doi.org/10.1117/12.327028
Event: Photonics East (ISAM, VVDC, IEMB), 1998, Boston, MA, United States

Abstract

To develop a cost-effective re-configurable DSP engine, it has been proposed to upgrade an existing custom designed TMS320C40 based multi-processing architecture with run-time configuration capabilities. The upgrade will consist of four Xilinx XC6200 series field programmable gate arrays which will enable concurrent algorithm structures to be efficiently mapped onto the system. Furthermore, the upgraded architecture will provide a platform for the development of adaptive routing structures, self- configuration techniques and facilitate the merging of instruction and hardware based parallelism.

Citation Download Citation

Ciaron W. Murphy, David Mark Harvey, and Laurence J. Nicolson "Low-cost reconfigurable DSP-based parallel image processing computer", Proc. SPIE 3526, Configurable Computing: Technology and Applications, (8 October 1998); https://doi.org/10.1117/12.327028

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