Architectural issues in VLIW video signal processors

Zhao Wu; Wayne H. Wolf

doi:10.1117/12.337417

22 January 1999 Architectural issues in VLIW video signal processors

Zhao Wu, Wayne H. Wolf

Proceedings Volume 3528, Multimedia Systems and Applications; (1999) https://doi.org/10.1117/12.337417
Event: Photonics East (ISAM, VVDC, IEMB), 1998, Boston, MA, United States

Abstract

As digital video becomes more prevalent, video signal processors (VSPs) emerge as a solution to accelerate computational-intensive multimedia applications. While dedicated VSPs are available for MPEG CODECs, the need for greater functionality and time-to-market pressures will push the video industry towards programmable VSPs. Combining a high degree of parallelism with the efficiency of statistically scheduled instructions, very long instruction word micro-architecture is becoming very popular and widely adopted. In this paper, we provide an overview of problems involved in VSP design, including hierarchical architectural paradigm, register and memory sizing, streaming computation, and so on. Analyses and solutions are also presented in addition to problem formulation. Understanding these problems well would help us realize architectural tradeoffs and pinpoint bottleneck in different stages of design sophistication.

Citation Download Citation

Zhao Wu and Wayne H. Wolf "Architectural issues in VLIW video signal processors", Proc. SPIE 3528, Multimedia Systems and Applications, (22 January 1999); https://doi.org/10.1117/12.337417

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