Reduction of postdevelop defects and process times for DUV lithography

Murthy S. Krishna; Emir Gurer; Ed C. Lee; Gary E. Flores; Sandra S. Ooka; John W. Salois; Royal Cherry; Reese M. Reynolds

doi:10.1117/12.350842

14 June 1999 Reduction of postdevelop defects and process times for DUV lithography

Murthy S. Krishna, Emir Gurer, Ed C. Lee, Gary E. Flores, Sandra S. Ooka, John W. Salois, Royal Cherry, Reese M. Reynolds

Author Affiliations +

Proceedings Volume 3677, Metrology, Inspection, and Process Control for Microlithography XIII; (1999) https://doi.org/10.1117/12.350842
Event: Microlithography '99, 1999, Santa Clara, CA, United States

Abstract

As the semiconductor industry moves into deeper sub-quarter micro regime, minimization of post develop process defects is of paramount significance in manufacturing environments. Reduce defects levels can significantly increase the yield in production, resulting in substantial cost savings and also reduce time to market of new devices. Typical approaches to reduce defect levels include extension of the DI rinse time immediately after completion of photoresists development, use of multiple rinse steps and variable rinse spin speed. However, many of these penalize the process throughput. The uniqueness of this project was the use of enhanced rinse hardware with a mechanistic understanding and characterization of defect generation for an advanced DUV resist.

Citation Download Citation

Murthy S. Krishna, Emir Gurer, Ed C. Lee, Gary E. Flores, Sandra S. Ooka, John W. Salois, Royal Cherry, and Reese M. Reynolds "Reduction of postdevelop defects and process times for DUV lithography", Proc. SPIE 3677, Metrology, Inspection, and Process Control for Microlithography XIII, (14 June 1999); https://doi.org/10.1117/12.350842

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