Process issues of sub-0.20-um contact hole patterns for logic devices and DRAM

Hyun-Jo Yang; Jin Young Yoon; Goo-Min Jeong; Hoon Huh; Jaejeong Kim

doi:10.1117/12.354389

26 July 1999 Process issues of sub-0.20-μm contact hole patterns for logic devices and DRAM

Hyun-Jo Yang, Jin Young Yoon, Goo-Min Jeong, Hoon Huh, Jaejeong Kim

Proceedings Volume 3679, Optical Microlithography XII; (1999) https://doi.org/10.1117/12.354389
Event: Microlithography '99, 1999, Santa Clara, CA, United States

Abstract

There are a number of process issues to take into account for patterning sub-0.20micrometers contact holes with optical lithography for Logic device or/and DRAM. Some of the most critical factors for patterning sub-0.20micrometers contact holes are discussed.

Citation Download Citation

Hyun-Jo Yang, Jin Young Yoon, Goo-Min Jeong, Hoon Huh, and Jaejeong Kim "Process issues of sub-0.20-μm contact hole patterns for logic devices and DRAM", Proc. SPIE 3679, Optical Microlithography XII, (26 July 1999); https://doi.org/10.1117/12.354389

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