A 50 to 400 Mbit/Sec Single Chip Fiber Optic Receiver Circuit

Dennis L. Rogers; Albert X Widmer; Joseph Mosley

doi:10.1117/12.941566

10 May 1984 A 50 to 400 Mbit/Sec Single Chip Fiber Optic Receiver Circuit

Dennis L. Rogers, Albert X Widmer, Joseph Mosley

Proceedings Volume 0466, Optical Interfaces for Digital Circuits & Systems; (1984) https://doi.org/10.1117/12.941566
Event: 1984 Los Angeles Technical Symposium, 1984, Los Angeles, United States

Abstract

A high speed fiber optic receiver is described which uses a single chip to perform all of the electronic functions. These functions include low noise preamplification, amplification to a logic compatible signal level, and automatic level restoration which maintains the correct receiver decision point over a large range of optical input power. The receiver has operated at bit rates from 50 to 400 Mbit/sec with sensitivities as high as -33 dbm.

Citation Download Citation

Dennis L. Rogers, Albert X Widmer, and Joseph Mosley "A 50 to 400 Mbit/Sec Single Chip Fiber Optic Receiver Circuit", Proc. SPIE 0466, Optical Interfaces for Digital Circuits & Systems, (10 May 1984); https://doi.org/10.1117/12.941566

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