Threshold logic parallel counters for 32-bit multipliers

Peter Celinski; Sorin D. Cotofana; Derek Abbott

doi:10.1117/12.477382

14 November 2002 Threshold logic parallel counters for 32-bit multipliers

Peter Celinski, Sorin D. Cotofana, Derek Abbott

Proceedings Volume 4935, Smart Structures, Devices, and Systems; (2002) https://doi.org/10.1117/12.477382
Event: SPIE's International Symposium on Smart Materials, Nano-, and Micro- Smart Systems, 2002, Melbourne, Australia

Abstract

In recent years, there has been renewed interest in Threshold Logic (TL), mainly as a result of the development of a number of successful implementations of TL gates in silicon. Threshold Logic enables, in some instances, the design of digital integrated circuits with a significantly reduced transistor count and area. This paper addresses the important problem of designing technologically feasible parallel (m,n) counters for using TL for binary multiplication. A number of counter design techniques are reviewed and some novel parallel counter designs are presented that allow the design of area efficient 32-bit multiplier partial product reduction circuits.

Citation Download Citation

Peter Celinski, Sorin D. Cotofana, and Derek Abbott "Threshold logic parallel counters for 32-bit multipliers", Proc. SPIE 4935, Smart Structures, Devices, and Systems, (14 November 2002); https://doi.org/10.1117/12.477382

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