Paper
24 May 2004 Usage of overlay metrology simulator in design of overlay metrology tools for the 65-nm node and beyond
Author Affiliations +
Abstract
The requirement for state-of-the-art performance by overlay metrology at the 65nm technology node drives the development and design of new optical metrology solutions. The use of measurement modeling is increasing, affecting the tool concepts, tolerances, and calibrations, as well as the overlay target design. In this article, we present our overlay metrology simulation platform, developed in-house, and its central role in optical performance modeling. The simulation validation tests are presented using standard overlay test wafers. The impact of residual optical aberrations with different overlay targets is simulated, emphasizing the degree of control needed to support overlay measurement methodology.
© (2004) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Yariv Simovitch R.N. and Shahar Gov "Usage of overlay metrology simulator in design of overlay metrology tools for the 65-nm node and beyond", Proc. SPIE 5375, Metrology, Inspection, and Process Control for Microlithography XVIII, (24 May 2004); https://doi.org/10.1117/12.535400
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Cited by 2 scholarly publications.
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KEYWORDS
Overlay metrology

Monochromatic aberrations

Semiconducting wafers

Silicon

Metrology

Point spread functions

Calibration

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