A hardware design on node in transport MPLS packet network based on FPGA

Wu Jia; Zhicheng Li; Zhihui Zhang; Juntao Liu; Xiaofei Li; Jialiang Zhang; Yongjun Zhang; Wanyi Gu

doi:10.1117/12.746121

19 November 2007 A hardware design on node in transport MPLS packet network based on FPGA

Wu Jia, Zhicheng Li, Zhihui Zhang, Juntao Liu, Xiaofei Li, Jialiang Zhang, Yongjun Zhang, Wanyi Gu

Proceedings Volume 6784, Network Architectures, Management, and Applications V; 678425 (2007) https://doi.org/10.1117/12.746121
Event: Asia-Pacific Optical Communications, 2007, Wuhan, China

Abstract

It Researches key technologies and hardware node structure of the Transport MPLS packet network. Main technology is super high speed FPGA. The transport plane adapts the layer 3 service signals from client equipments and forwards them. There are two types of node in transport plane, edge node (EN) or core node (CN), and the nodes realized with large-scale FPGA chip have three main function units and six types of board. The EN adapts the layer 3 service signals such as TDM, Packet and Cell to TM signals by add shim. The CN is responsible for the TM signals switching in higher speed than traditional packet network such as Ethernet. Control plane is embedded in a FPGA chip and designed based on the ASON core technique (GMPLS) such as the transport label switching path (T-LSP) maintaining (set up, release, state monitoring), route controlling and protect recovering and so on.

Citation Download Citation

Wu Jia, Zhicheng Li, Zhihui Zhang, Juntao Liu, Xiaofei Li, Jialiang Zhang, Yongjun Zhang, and Wanyi Gu "A hardware design on node in transport MPLS packet network based on FPGA", Proc. SPIE 6784, Network Architectures, Management, and Applications V, 678425 (19 November 2007); https://doi.org/10.1117/12.746121

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