Dynamically reconfigurable router for NoC congestion reduction

Juan E. Rosales; Félix Tobajas; Valentín de Armas; José A. Mori; Roberto Sarmiento

doi:10.1117/12.887473

3 May 2011 Dynamically reconfigurable router for NoC congestion reduction

Juan E. Rosales, Félix Tobajas, Valentín de Armas, José A. Mori, Roberto Sarmiento

Proceedings Volume 8067, VLSI Circuits and Systems V; 80670H (2011) https://doi.org/10.1117/12.887473
Event: SPIE Microtechnologies, 2011, Prague, Czech Republic

Abstract

Multiprocessor System-on-Chip (MPSoCs) are emerging as one of the technologies providing a way to support the growing design complexity of embedded systems including several types of cores. The interconnection among cores of a MPSoC is proposed to be provided by Networks-on-Chip (NoC). In real applications it is usual to find different interconnection needs amongst cores, so distinct bandwidth is needed in each node of a NoC. Since larger FIFOs in NoC routers provide larger throughputs and smaller latencies, depths are usually sized for the worst case, compromising not only the routing area, but power consumption. In this paper, a reconfigurable router with a dynamic sharing mechanism of buffers at the input channels is proposed to reduce congestion in the network. In this situation, a channel may dynamically lend or borrow some non-used buffer units to or from neighboring channels, in accordance to the connection rates. The proposed reconfigurable router architecture was embedded in the Hermes NoC. The main advantages of the Hermes are its small size and modular design. This, as well as the open source approach, have lead to the selection of this NoC. The basic element of Hermes is a router with five bi-directional ports employing an XY routing algorithm. FIFO buffering is present only at the input channel, with all channels having the same buffer depth defined at design time. The proposed reconfigurable router has been coded in VHDL at RTL level from the adaptation of the Hermes router to fit into the proposed scheme. Results obtained from the simulation of the router under scenarios with different traffic characteristics and percentage of shared buffer, show that mean latency can be reduced up to a 30% in comparison to the original router.

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Juan E. Rosales, Félix Tobajas, Valentín de Armas, José A. Mori, and Roberto Sarmiento "Dynamically reconfigurable router for NoC congestion reduction", Proc. SPIE 8067, VLSI Circuits and Systems V, 80670H (3 May 2011); https://doi.org/10.1117/12.887473

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KEYWORDS

Network on a chip

Signal processing

Switches

Clocks

Process control

Switching

Data storage

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