Design of bit error rate tester based on a high speed bit and sequence synchronization

Xuanmin Wang; Xiangmo Zhao; Lichuan Zhang; Yinglong Zhang

doi:10.1117/12.2010928

14 March 2013 Design of bit error rate tester based on a high speed bit and sequence synchronization

Xuanmin Wang, Xiangmo Zhao, Lichuan Zhang, Yinglong Zhang

Proceedings Volume 8768, International Conference on Graphic and Image Processing (ICGIP 2012); 876832 (2013) https://doi.org/10.1117/12.2010928
Event: 2012 International Conference on Graphic and Image Processing, 2012, Singapore, Singapore

Abstract

In traditional BER（Bit Error Rate) tester, bit synchronization applied digital PLL and sequence synchronization utilized sequence's correlation.It resulted in a low speed on bit and sequence synchronization. this paper came up new method to realize bit and sequence synchronization .which were Bit-edge-tracking method and Immitting-sequence method.The BER tester based on FPGA was designed.The functions of inserting error-bit and removing the false sequence synchronization were added. The results of Debuging and simulating display that the time to realize bit synchronization is less than a bit width, the lagged time of the tracking bit pulse is 1/8 of the code cycle,and there is only a M sequence's cycle to realize sequence synchronization.This new BER tester has many advantages,such as a short time to realize bit and sequence synchronization,no false sequence synchronization,testing the ability of the receiving port's error -correcting and a simple hareware.

Citation Download Citation

Xuanmin Wang, Xiangmo Zhao, Lichuan Zhang, and Yinglong Zhang "Design of bit error rate tester based on a high speed bit and sequence synchronization", Proc. SPIE 8768, International Conference on Graphic and Image Processing (ICGIP 2012), 876832 (14 March 2013); https://doi.org/10.1117/12.2010928

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