A Practical Real Time Svd Machine With Multi-Level Fault Tolerance

David E. Schimmel; Franklin T. Luk

doi:10.1117/12.976256

23 March 1986 A Practical Real Time Svd Machine With Multi-Level Fault Tolerance

David E. Schimmel, Franklin T. Luk

Proceedings Volume 0698, Real-Time Signal Processing IX; (1986) https://doi.org/10.1117/12.976256
Event: 30th Annual Technical Symposium, 1986, San Diego, United States

Abstract

A fault tolerant systolic processor system is proposed for computing the singular value decomposition of an nxn matrix. This approach uses only orthogonal interconnections and simple multiply and accumulate processors in the array. The fault tolerant properties are achieved through a composite of simple low overhead structures. The square root computations, and all fault tolerance computations are performed in one highly pipelined boundary processor. The architecture requires 0(n) processors and 0(n2 log n) time.

Citation Download Citation

David E. Schimmel and Franklin T. Luk "A Practical Real Time Svd Machine With Multi-Level Fault Tolerance", Proc. SPIE 0698, Real-Time Signal Processing IX, (23 March 1986); https://doi.org/10.1117/12.976256

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