High Speed Device Testing And Internal Node Diagnostics

George Chiu; Jean-Marc Halbout; Paul May

doi:10.1117/12.940385

1 September 1987 High Speed Device Testing And Internal Node Diagnostics

George Chiu, Jean-Marc Halbout, Paul May

Proceedings Volume 0774, Lasers in Microlithography; (1987) https://doi.org/10.1117/12.940385
Event: Microlithography Conferences, 1987, Santa Clara, CA, United States

Abstract

The performance of micron and submicron devices and chips for the coming decade is advancing at a rapid pace. The requirements to test these ultrafast, small, and dense circuits give rise to great challenges for high speed testing. Methodology to meet these challenges and yet unsolved forthcoming problems are discussed.

Citation Download Citation

George Chiu, Jean-Marc Halbout, and Paul May "High Speed Device Testing And Internal Node Diagnostics", Proc. SPIE 0774, Lasers in Microlithography, (1 September 1987); https://doi.org/10.1117/12.940385

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