Equalizing Si photodetectors fabricated in standard CMOS processes

E. Guerrero; J. Aguirre; C. Sánchez-Azqueta; G. Royo; C. Gimeno; S. Celma

doi:10.1117/12.2264603

30 May 2017 Equalizing Si photodetectors fabricated in standard CMOS processes

E. Guerrero, J. Aguirre, C. Sánchez-Azqueta, G. Royo, C. Gimeno, S. Celma

Proceedings Volume 10249, Integrated Photonics: Materials, Devices, and Applications IV; 102490N (2017) https://doi.org/10.1117/12.2264603
Event: SPIE Microtechnologies, 2017, Barcelona, Spain

Abstract

This work presents a new continuous-time equalization approach to overcome the limited bandwidth of integrated CMOS photodetectors. It is based on a split-path topology that features completely decoupled controls for boosting and gain; this capability allows a better tuning of the equalizer in comparison with other architectures based on the degenerated differential pair, which is particularly helpful to achieve a proper calibration of the system. The equalizer is intended to enhance the bandwidth of CMOS standard n-well/p-bulk differential photodiodes (DPDs), which falls below 10MHz representing a bottleneck in fully integrated optoelectronic interfaces to fulfill the low-cost requirements of modern smart sensors. The proposed equalizer has been simulated in a 65nm CMOS process and biased with a single supply voltage of 1V, where the bandwidth of the DPD has been increased up to 3 GHz.

Citation Download Citation

E. Guerrero, J. Aguirre, C. Sánchez-Azqueta, G. Royo, C. Gimeno, and S. Celma "Equalizing Si photodetectors fabricated in standard CMOS processes", Proc. SPIE 10249, Integrated Photonics: Materials, Devices, and Applications IV, 102490N (30 May 2017); https://doi.org/10.1117/12.2264603

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