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20 February 2018 FPGA implementation of full parallel LDPC encoder
Zhaohui Wang, Xin Hao, Yujiao Zhao
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Proceedings Volume 10697, Fourth Seminar on Novel Optoelectronic Detection Technology and Application; 1069751 (2018) https://doi.org/10.1117/12.2307062
Event: Fourth Seminar on Novel Optoelectronic Detection Technology and Application, 2017, Nanjing, China
Abstract
This paper gives a detailed introduction to the FPGA implementation of Full Parallel Low-Density ParityCheck(LDPC) Encoder, which is designed base on Richardson-Urbanke Algorithm with a code length 4096, code rate 4/5 on CCSDS standard. The proposed design use LUTs to solve matrix multiplication with low-complexity, the encode result can output in 4 clocks, the speed of the encoder can be higher than 6.4 Gbps, and the resource utilization is acceptable.
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Zhaohui Wang, Xin Hao, and Yujiao Zhao "FPGA implementation of full parallel LDPC encoder", Proc. SPIE 10697, Fourth Seminar on Novel Optoelectronic Detection Technology and Application, 1069751 (20 February 2018); https://doi.org/10.1117/12.2307062
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KEYWORDS
Computer programming
Field programmable gate arrays
Matrices
Computer architecture
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