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The need for low-cost, real-time, image processing for automated inspection and other industrial applications has led to considerable effort being directed at many novel computer architectures. Two main avenues of work have become apparent: the use of powerful parallel architectures and the use of pipelined processors. The former while offering great flexibility, have, to date, been associated with high cost. The latter, being essentially simpler processors can produce considerable cost savings but have generally been inflexible and provided a limited number of functions. Pipeline processors have generally found application as pre-processors for use with parallel machines or in image enhancement for human operators where relatively simple processing is required. The paper describes the development of an adaptive pipeline processor which offers the potential cost efficiency of large scale integration together with the flexibility of an adaptive system. The processor concerned accepts digitised video information from any standard video source and performs real-time processing on it. Each identical processor element (PE) can be programmed by a separate controller over a high speed communications channel, and can perform a range of operations including filtering, averaging, edge-detection, line-thinning, thresholding, scaling and inversion. Synchronisation information is also processed by the PE allowing any number of elements to be cascaded without the need for a frame store. A typical image processing arrangement would consist of a series of identical PEs connected in series and a separate control computer which is responsible for configuring the system. The absence of frame buffering within the system greatly reduces its cost and provides true real-time operation. Since each PE may be reconfigured in real-time the parameters and functions of each element can be modified to suit the image. This permits the processing to be adapted to cater for changing lighting conditions or a change of scene. Since each PE will be implemented as a single, identical, VLSI circuit, the arrangement is potentially very cost effective.
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