A comparison and study of low power comparator design techniques

Kehan Huang; Lingyi Jiang; Yanda Qu

doi:10.1117/12.2639408

19 October 2022 A comparison and study of low power comparator design techniques

Kehan Huang, Lingyi Jiang, Yanda Qu

Proceedings Volume 12294, 7th International Symposium on Advances in Electrical, Electronics, and Computer Engineering; 122941I (2022) https://doi.org/10.1117/12.2639408
Event: 7th International Symposium on Advances in Electrical, Electronics and Computer Engineering (ISAEECE 2022), 2022, Xishuangbanna, China

Abstract

Low-power is a key technical indicator in the design of the comparator. This article discusses several different designs and techniques for achieving low power consumption. In this article, there are two different ways to achieve the goal. One is to transform the preamplifier of the comparator to realize low energy utilization. Such as using a tail capacitor with dynamic bias or adopting an inverter-based input pair. The other is to redesign the traditional comparator structure. For example, an edge-pursuit comparator and a high-performance dynamic comparator with a new latching stage. Due to the adjustment of different design parameters, the comparator also has advantages in terms of noise, delay, and gain.

Citation Download Citation

Kehan Huang, Lingyi Jiang, and Yanda Qu "A comparison and study of low power comparator design techniques", Proc. SPIE 12294, 7th International Symposium on Advances in Electrical, Electronics, and Computer Engineering, 122941I (19 October 2022); https://doi.org/10.1117/12.2639408

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