Constructing layout hierarchy for high-efficiency OPC flow

Tsung-Wei Lin; Hung-Yu Lin; Mang-Shiun Chiang; Shi-Cheng Yeh; Jason Sweis; Philippe Hurat; Tung-Yu Wu; Chun-Sheng Wu; Chao-Yi Huang; Ya-Chieh Lai

doi:10.1117/12.2657649

28 April 2023 Constructing layout hierarchy for high-efficiency OPC flow

Tsung-Wei Lin, Hung-Yu Lin, Mang-Shiun Chiang, Shi-Cheng Yeh, Jason Sweis, Philippe Hurat, Tung-Yu Wu, Chun-Sheng Wu, Chao-Yi Huang, Ya-Chieh Lai

Author Affiliations +

Proceedings Volume 12495, DTCO and Computational Patterning II; 124951N (2023) https://doi.org/10.1117/12.2657649
Event: SPIE Advanced Lithography + Patterning, 2023, San Jose, California, United States

Abstract

Optical Proximity Correction (OPC) is an important step in the optical lithography-based manufacturing process. Starting from 115 nm, lithography processes typically use OPC to resolve features acceptably. Advanced OPC technologies use model-based edge segment adjustments to achieve highly accurate corrections. The typical process for optical proximity correction suffers from a huge turn-around-time (TAT) and is well known to have time-consuming complexity especially at 40 nm and below. Therefore, in order to speed up process development and increase qualified pattern variations with good yield, we must find ways to speed up the OPC TAT. This paper presents a flow to construct layout hierarchy and increase OPC cell/template re-use to greatly reduce the OPC TAT using the Pegasus Computational Pattern Analytics (CPA) software.

Citation Download Citation

Tsung-Wei Lin, Hung-Yu Lin, Mang-Shiun Chiang, Shi-Cheng Yeh, Jason Sweis, Philippe Hurat, Tung-Yu Wu, Chun-Sheng Wu, Chao-Yi Huang, and Ya-Chieh Lai "Constructing layout hierarchy for high-efficiency OPC flow", Proc. SPIE 12495, DTCO and Computational Patterning II, 124951N (28 April 2023); https://doi.org/10.1117/12.2657649

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