Low-power approximate multipliers for artificial intelligence chips

Hui Xiao

doi:10.1117/12.2682332

20 June 2023 Low-power approximate multipliers for artificial intelligence chips

Hui Xiao

Proceedings Volume 12715, Eighth International Conference on Electronic Technology and Information Science (ICETIS 2023); 127151S (2023) https://doi.org/10.1117/12.2682332
Event: Eighth International Conference on Electronic Technology and Information Science (ICETIS 2023), 2023, Dalian, China

Abstract

With the rapid development of deep learning-based neural network models, traditional general-purpose chips can hardly meet the needs of large-scale neural network computing tasks, so artificial intelligence chips come out along with the trend. In the application area of artificial intelligence chips, many computational tasks are related to multiplication, and multipliers are used very frequently. Due to the complexity and optimizability of multipliers themselves, their approximate design can effectively reduce the power consumption and improve the computational power of artificial intelligence chips. In this paper, we design two approximate multipliers based on Karatsuba algorithm and radix-8 booth multiplication, which reduce the power consumption by more than 45% and can be well adapted to various different neural network models to replace the exact multiplication unit of artificial intelligence chips.

Citation Download Citation

Hui Xiao "Low-power approximate multipliers for artificial intelligence chips", Proc. SPIE 12715, Eighth International Conference on Electronic Technology and Information Science (ICETIS 2023), 127151S (20 June 2023); https://doi.org/10.1117/12.2682332

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