The throughput of error correction is one of the main bottlenecks of high-speed continuous variable quantum key distribution (CV-QKD) post-processing, which directly restricts the practical secret key rates (SKR). Implementing the decoder of low-density parity-check (LDPC) codes based on FPGA in limited precision can improve the decoding throughput significantly. In this paper, a high-throughput decoder architecture with limited precision for quasi-cyclic LDPC (QC-LDPC) codes is proposed. In particular, decoding of two typical LDPC codes, with code rates 0.2 and 0.1, for CV-QKD have been implemented on a commercial FPGA. The clock operates at 100 MHZ and the throughput of 1.44 Gbps and 0.78 Gbps is achieved, respectively, which can support 71.89 Mbps and 9.97 Mbps real-time SKR under transmission distance of 25 km and 50 km, respectively. The proposed architecture paves the way for high-rate real-time CV-QKD deployment in secure metropolitan area network.
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