Yield enhancement through identifying design sensitivities

Bei Tseng Bill Chu; Mark D. Kellam

doi:10.1117/12.21150

1 January 1990 Yield enhancement through identifying design sensitivities

Bei Tseng Bill Chu, Mark D. Kellam

Proceedings Volume 1293, Applications of Artificial Intelligence VIII; (1990) https://doi.org/10.1117/12.21150
Event: 1990 Technical Symposium on Optics, Electro-Optics, and Sensors, 1990, Orlando, FL, United States

Abstract

It is commonly recognized that there are three main causes of circuit yield losses: process related problems, design sensitivities, and point defects. Yield losses due to design sensitivity primarily occur during the early development phase of a VLSI circuit. Previous work in eliminating design sensitivities have concentrated on using statistical simulations which is computationally expensive for VLSI circuits with over million transistors. This paper describes an approach to detect design sensitivity using methods of pattern recognition and parsimonious hypothesis formation.

Citation Download Citation

Bei Tseng Bill Chu and Mark D. Kellam "Yield enhancement through identifying design sensitivities", Proc. SPIE 1293, Applications of Artificial Intelligence VIII, (1 January 1990); https://doi.org/10.1117/12.21150

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