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A new application in the semiconductor industry that received quite some traction the past few years is bringing the transistor power delivery network to the backside of the wafer. The big gain of this change is that it frees up real estate on the frontside of the wafer, enabling a further increase of the transistor density. This so-called Back-Side Power Delivery Network (BS-PDN) application is quite challenging since it requires a direct wafer-to-wafer bonding process module. To get access to the transistor from the backside, a device wafer needs to be flipped and bonded to a carrier wafer followed by an annealing step. After these processing steps, the original substrate of the device wafer is removed by grinding and etch steps. This will enable access to the transistors from the backside of the wafer. The wafer processing continues by conventional layer deposition, lithography and etch steps, this time on the flipped wafer. Unfortunately, the bonding process module that includes the actual direct wafer-to-wafer bonding step itself, will also introduce a distortion in the device layer that has been transferred to the carrier wafer. Since the on-product overlay requirement for the first exposed layer on the backside to one of the front-side layers is tight (<10-nm today and <<5-nm in the foreseeable future), a deep understanding of the origin of the distortion fingerprint after bonding is required. In our previous work, we presented a method to isolate the distortion fingerprint due to bonding from the remaining other overlay contributors. The fingerprint we observed after linear corrections had a typical magnitude ranging from 50 to 80-nm. A clear 4-fold symmetry was observed that could be attributed to the crystal orientation of the (100) silicon substrate. We demonstrated that the scanner wafer alignment model is very capable of correcting the global 4-fold wafer distortion fingerprint. Residual levels of less than ~15-nm were shown. These residuals could be further reduced by applying a correction per exposure (CPE) recipe. We showed that performance levels of less than ~6-nm (99.7%) and ~10-nm (max) could be achieved after a 33-parameter per exposure field self-correction. The resulting wafer plots nicely revealed how to improve the overlay performance further. An increased level of residuals was found in the wafer center and at the wafer edge. In the current paper, we build upon our previous work and continue the investigation on the remaining overlay contributors that were identified previously. This time, the focus will be on the local wafer deformations that are visible after the direct wafer-to-wafer bonding step. By local we mean the distortions that manifest themselves over a very short spatial range. These local distortions cannot easily be corrected by the scanner and are typically present close to the wafer center and the wafer edge. We know that the local wafer deformation close to the wafer center is caused by the bonding pin that initiates the bond wave. To characterize the center distortion signature, we varied many experimental parameters to see the impact. We will show the impact of the die layout, the rotation of the top wafer by a 45-degrees, wafer surface properties, and substrate choice of the carrier wafer. The latter is interesting, we evaluated both (100) and (111) carrier wafers. Although the prime focus will be to improve the overlay performance on the center of the wafer, we monitor the impact of the experimental settings on the wafer edge and remaining part of the wafer as well. We present a path forward to mitigate the local distortions such that they will not be blocking for high volume production.
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