High performance and low area interconnect structure based on AXI

Yahan Zhang; Gang Cai; Zhihong Huang

doi:10.1117/12.3015622

16 January 2024 High performance and low area interconnect structure based on AXI

Yahan Zhang, Gang Cai, Zhihong Huang

Proceedings Volume 12973, Workshop on Electronics Communication Engineering (WECE 2023); 1297306 (2024) https://doi.org/10.1117/12.3015622
Event: Workshop on Electronics Communication Engineering (WECE 2023), 2023, Guilin, China

Abstract

As the scale of high-performance System-on-Chip (SoC) continues to grow, the need for frequent data exchange among various Intelligent Property (IP) cores such as processors, memories, and peripherals becomes crucial. However, existing on-chip bus structures often compromise area and complexity to enhance performance for accommodating the data transfer requirements of complex SoCs. In this study, we propose a high performance, low area interconnect architecture based on the Advanced eXtensible Interface(AXI) bus specification, which can be effectively utilized in conjunction with several processors to construct efficient and compact embedded SoC. The proposed design employs a hierarchical approach for read and write operations to minimize area consumption and resource utilization. For read and write transactions, a shared address bus and a shared data bus structures are utilized, respectively, to support synchronous read and write operations. Additionally, to enhance the data transfer capability and reliability of the interconnect, our approach involves the utilization of weighted arbiters for prioritization and the implementation of random access queues as a caching mechanism. Experimental results demonstrate that this design enables efficient data transfer with exceptional performance and scalability, while maintaining the benefits of reduced area and complexity.

(2024) Published by SPIE. Downloading of the abstract is permitted for personal use only.

Citation Download Citation

Yahan Zhang, Gang Cai, and Zhihong Huang "High performance and low area interconnect structure based on AXI", Proc. SPIE 12973, Workshop on Electronics Communication Engineering (WECE 2023), 1297306 (16 January 2024); https://doi.org/10.1117/12.3015622

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available