Design of LDO circuit with low noise and high PSRR

Xiao Li; Shengming Huang; Yingying Yao

doi:10.1117/12.3030321

5 June 2024 Design of LDO circuit with low noise and high PSRR

Xiao Li, Shengming Huang, Yingying Yao

Proceedings Volume 13163, Fourth International Conference on Mechanical, Electronics, and Electrical and Automation Control (METMS 2024); 131633H (2024) https://doi.org/10.1117/12.3030321
Event: International Conference on Mechanical, Electronics, and Electrical and Automation Control (METMS 2024), 2024, Xi'an, China

Abstract

Power supply rejection ratio (PSRR) and noise are important parameters of low voltage difference linear regulators (LDO), which are widely used in audio circuits. In order to achieve high PSRR and low noise, PSRR enhancement circuit and filter circuit are introduced in the LDO circuit designed in this paper. The LDO circuit designed in this paper is realized by MGN 0.35um process. The simulation analysis of the circuit by Cadence tool shows that the PSRR of the LDO circuit is -79dB at low frequency, which is better than -60dB at high frequency. The output noise is 0.395 uv/ √Hz at 1KHz, and the noise in the frequency range of 10Hz~100 KHz is as low as 32.5uVRMS.

(2024) Published by SPIE. Downloading of the abstract is permitted for personal use only.

Citation Download Citation

Xiao Li, Shengming Huang, and Yingying Yao "Design of LDO circuit with low noise and high PSRR", Proc. SPIE 13163, Fourth International Conference on Mechanical, Electronics, and Electrical and Automation Control (METMS 2024), 131633H (5 June 2024); https://doi.org/10.1117/12.3030321

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