Paper
1 November 1990 FFT communications requirement optimizations on massively parallel architectures with local and global interprocessor communications capabilities
Christopher L. Kuszmaul
Author Affiliations +
Abstract
Fast Fourier Transforms [1] Batcher sorting [2] Cyclic Reduction [3] and a host of other recursively defined divide and conquer style algorithms can be implemented on massively parallel computers which provide for rapid communications between data elements whose indices differ by a power of two. This paper addresses the general issue of how two different communication mechanisms one Global and one Local can provide for hybrid performance that substantially exceeds what either could provide separately. In particular power of two communications schemes are explored for the MP-1 family ofmassively parallel computers. By using a combination of the eight way nearest neighbor toroidally wrapped grid and the Global Router on an MP-1 1200 series computer with 16 processors (PEs) the communications requirements for a 16 point FFT are shown to require less than 2 milliseconds.
© (1990) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Christopher L. Kuszmaul "FFT communications requirement optimizations on massively parallel architectures with local and global interprocessor communications capabilities", Proc. SPIE 1348, Advanced Signal Processing Algorithms, Architectures, and Implementations, (1 November 1990); https://doi.org/10.1117/12.23497
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KEYWORDS
Computing systems

Data communications

Fourier transforms

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