High Tc superconducting digital gates

Roger Davidheiser

doi:10.1117/12.2321841

1 March 1992 High Tc superconducting digital gates

Roger Davidheiser

Proceedings Volume 1597, Progress in High-Temperature Superconducting Transistors and Other Devices II; (1992) https://doi.org/10.1117/12.2321841
Event: Microelectronic Processing Integration, 1991, San Jose, CA, United States

Abstract

Superconducting digital gates promise high speed performance at exceedingly low power. Thus, if this technology meets acceptance in packing density, integration levels, margins, and ease of design, it will be extremely competitive. TRW has recently reported the first digital gates in the new high temperature superconducting material YBaCuO. The gates are embedded in a novel architecture that achieves an ease of design and resembles the circuitry employed by the CMOS community. Thus not only will the circuitry operate with convenient minature cryocoolers supporting 65K, but a large group of designers will aid the development. As well the architecture supports gate array development procedures. We report the Boolean functions of AND, EXOR, EXNOR, inversion and buffer gates developed at low speed and reduced temperature. Modelling of newer devices allready available to us predicts operation at up to a 1 GHz clock and at 50K. The additional functions of NAND, NOR, and OR are modifications of the final wiring layer on the basic gate design.

Citation Download Citation

Roger Davidheiser "High Tc superconducting digital gates", Proc. SPIE 1597, Progress in High-Temperature Superconducting Transistors and Other Devices II, (1 March 1992); https://doi.org/10.1117/12.2321841

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