Methodology for generating behavioral specifications of analog hardware for artificial neural network implementations

Arun Achyuthan; Mohamed I. Elmasry

doi:10.1117/12.152569

2 September 1993 Methodology for generating behavioral specifications of analog hardware for artificial neural network implementations

Arun Achyuthan, Mohamed I. Elmasry

Author Affiliations +

Proceedings Volume 1965, Applications of Artificial Neural Networks IV; (1993) https://doi.org/10.1117/12.152569
Event: Optical Engineering and Photonics in Aerospace Sensing, 1993, Orlando, FL, United States

Abstract

The non-ideal behavior of analog integrated circuits make it necessary that Artificial Neural Network (ANN) systems be evaluated for the effect of error due to the non-idealities on its performance, before they are implemented in analog hardware. In this paper we describe a procedure for automatically evaluating a given ANN system, described in the form of a Data Flow Graph (DFG). The equations required for the quantitative evaluation are extracted from the DFG description using symbolic computation techniques. Optimization methods are applied for generating bounds on the maximum values of error that can be associated with each circuit block. The generated bounds are put back to behavioral models of individual circuits blocks in the design library, to help screening viable alternatives and to generate circuit level specifications. The methodology forms part of a design automation environment that helps to map ANN systems to hardware interconnection descriptions.

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Arun Achyuthan and Mohamed I. Elmasry "Methodology for generating behavioral specifications of analog hardware for artificial neural network implementations", Proc. SPIE 1965, Applications of Artificial Neural Networks IV, (2 September 1993); https://doi.org/10.1117/12.152569

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