Paper
9 November 1993 Implementing neural nets on non-ideal analog hardware
Leonard Neiberg, David P. Casasent
Author Affiliations +
Abstract
We consider the implementation of high capacity Ho-Kashyap associative processors on non- ideal optical and analog VLSI systems. Processor non-idealities considered include quantization, non-uniform beam illumination, and nonlinear device characteristics. New training-out techniques to overcome these non-idealities are advanced. We obtain optimal performance in the presence of stochastic noise by proper selection of the processor parameter (sigma) syn. We derive important results that allow us to a priori determine the optimal value of (sigma) syn and the expected recall accuracy P'c without having to simulate the specific processor. We present a new algorithm that allow us to achieve storage near the theoretical maximum capacity (2N, where N is the dimensionality of the input vector) with excellent recall accuracy. Optical laboratory results are included. We achieved storage of 1.5 N with recall accuracy P'c >= 95% with input noise of standard deviation (omega) 1 equals 0.02 present and with optical analog components with 5 bit input accuracy and 8 bit memory matrix accuracy. With higher accuracy analog VLSI components (10 bit input accuracy and 11 bit weight accuracy), we achieve storage of 1.75 N with P'c equals 96.43%.
© (1993) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Leonard Neiberg and David P. Casasent "Implementing neural nets on non-ideal analog hardware", Proc. SPIE 2026, Photonics for Processors, Neural Networks, and Memories, (9 November 1993); https://doi.org/10.1117/12.163598
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KEYWORDS
Analog electronics

Very large scale integration

Quantization

Error analysis

Neurons

Stochastic processes

Neural networks

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