Low-cost hardware acceleration for volume visualization

Michael Dao; Todd A. Cook; Deborah E. Silver

doi:10.1117/12.221329

19 September 1995 Low-cost hardware acceleration for volume visualization

Michael Dao, Todd A. Cook, Deborah E. Silver

Proceedings Volume 2607, Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing; (1995) https://doi.org/10.1117/12.221329
Event: Photonics East '95, 1995, Philadelphia, PA, United States

Abstract

Volume visualization is a popular method for viewing simulated or experimental 3D data sets from applications such as medical imaging, computational fluid dynamics, and climate modeling. However, most software and low-cost hardware implementations of visualization algorithms do not have sufficient performance for inter-active viewing. This paper discusses a method for low-cost, parallel hardware acceleration of volume rendering using a PC-hosted FPGA board. Our method uses a parallel distributed memory approach for compositing and tranformation of volume data, and it provides insight into efficient use of low-cost memory systems.

Citation Download Citation

Michael Dao, Todd A. Cook, and Deborah E. Silver "Low-cost hardware acceleration for volume visualization", Proc. SPIE 2607, Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing, (19 September 1995); https://doi.org/10.1117/12.221329

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