Programmable real-time FIR-filter logic device

Eduardo I. Boemo; F. Barbero; J. Faura; J. Jauregui; J. M. Meneses

doi:10.1117/12.221343

19 September 1995 Programmable real-time FIR-filter logic device

Eduardo I. Boemo, F. Barbero, J. Faura, J. Jauregui, J. M. Meneses

Proceedings Volume 2607, Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing; (1995) https://doi.org/10.1117/12.221343
Event: Photonics East '95, 1995, Philadelphia, PA, United States

Abstract

This paper resumes the development of an integrate tool for designing high-speed, real-time, FIR-filter circuits. The system is composed of programmable IC and an associate software for filter repsonse analysis, synthesis of coefficients, and circuit programming. The architecture is highly regular, easily expandable and its control is distributed. The chip can be programmed by a PC or by using an EPROM. The prototypes have been fabricated using the CMOS 1.5micrometers Standard Cell of ES2. Moreover, some heuristics about multipliers upgrated to CMOS 1micrometers - Cadence DFWII are resumed.

Citation Download Citation

Eduardo I. Boemo, F. Barbero, J. Faura, J. Jauregui, and J. M. Meneses "Programmable real-time FIR-filter logic device", Proc. SPIE 2607, Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing, (19 September 1995); https://doi.org/10.1117/12.221343

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