Paper
1 December 1995 Digital cyphering system using chaos time series
Hajime Takakubo, Katsufusa Shono
Author Affiliations +
Proceedings Volume 2612, Chaotic Circuits for Communication; (1995) https://doi.org/10.1117/12.227905
Event: Photonics East '95, 1995, Philadelphia, PA, United States
Abstract
A voltage-mode CMOS looped circuit generates complex chaos time series, and it is digitized by an AD converter. The digitized time series of internal state shows an irreversible multiple complexity in the past, due to bifurcation. The multiple complexity of internal states in chaos time series is utilized as a scramble code in a digital ciphering system. A binary coded information is bit-serially converted into a corresponding scramble code. An average conversion rate of the ciphering system using 8-bit data base is 102 k bit/sec. On the other hand, the internal states in the future time series are quite deterministic, even if it has multiple internal states in the past. The scramble code can be decoded by the deterministic phenomenon.
© (1995) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Hajime Takakubo and Katsufusa Shono "Digital cyphering system using chaos time series", Proc. SPIE 2612, Chaotic Circuits for Communication, (1 December 1995); https://doi.org/10.1117/12.227905
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Cited by 2 scholarly publications.
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KEYWORDS
Chaos

Binary data

Analog electronics

Error analysis

Data conversion

Clocks

Digital electronics

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