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We report on a reconfigurable optical interconnection approach in which static communication graphs are extracted from high level programs and are mapped onto a two stage optical beam-steered/perfect shuffle interconnect. An array of processing elements (PEs) is partitioned into functional units of equal size that are served by one optical input/output (I/O) port per PE. PEs within a functional unit can use any of the optical I/O ports served by that functional unit. An optical beam-steering mechanism in conjunction with an optical perfect shuffle interconnects the functional units. At the highest level, computer programs are written in the Id dataflow programming language. At the next level, dataflow graphs (communication graphs that represent the natural parallelism in a computation) are automatically extracted from the high-level programs. At the lowest level, the dataflow graphs are mapped onto the optical beam-steered/perfect shuffle interconnect. This mapping step is facilitated by a mechanism that redirects optical beams to that the physical interconnect takes the form of the dataflow graph. An intended application is to create low latency realizations of specialized hardware on-the-fly, such as for rapid prototyping. An advantage of this approach over competing all-electronic or static free-space optical interconnection approaches is that the optical interconnect has low depth (two stages) with low fan-out (typically 1 to 3). In previous work, the behaviors of the mappings are studied for randomly generated dataflow graphs. In the work reported here, the behaviors of the mappings are studied for extracted dataflow graphs. We conclude that this interconnection approach is effective for extracted dataflow graphs, using only a single pass through the network, if the interconnect is augmented with a small crossbar within each functional unit.
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