Process optimization for sub-100-nm gate patterns using phase edge lithography

Koen van Ingen Schenau; Bert Vleeming; Wendy F.J. Gehoel-van Ansem; Patrick Wong; Geert Vandenberghe

doi:10.1117/12.436849

24 August 2001 Process optimization for sub-100-nm gate patterns using phase edge lithography

Koen van Ingen Schenau, Bert Vleeming, Wendy F.J. Gehoel-van Ansem, Patrick Wong, Geert Vandenberghe

Proceedings Volume 4345, Advances in Resist Technology and Processing XVIII; (2001) https://doi.org/10.1117/12.436849
Event: 26th Annual International Symposium on Microlithography, 2001, Santa Clara, CA, United States

Abstract

This paper investigates the impact of photoresist on sub- 100nm gate patterning performance using phase edge lithography. A selection of mostly commercial photoresists for both the 193nm and 248nm wavelength were compared for pattern collapse and photoresist profiles. An acrylic type 193nm photoresist yielded the largest aspect ratio; straight 50nm isolated lines were printed in 330 nm thick photoresist. The optimization for CD uniformity was driven by the isofocal position being dependent on photoresist characteristics, mask design parameters, and illumination conditions. The photoresists with low isofocal CD improved CD control except for mask designs using small phase widths. The optimized 193nm process yielded a 3(sigma) of 6nm CD uniformity over 400nm focus range for 70nm isolated lines when exposed on a PAS5500/950 Step&Scan system.

Citation Download Citation

Koen van Ingen Schenau, Bert Vleeming, Wendy F.J. Gehoel-van Ansem, Patrick Wong, and Geert Vandenberghe "Process optimization for sub-100-nm gate patterns using phase edge lithography", Proc. SPIE 4345, Advances in Resist Technology and Processing XVIII, (24 August 2001); https://doi.org/10.1117/12.436849

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