High-performance VLSI architecture for video processing

Hector Navarro; Juan A. Montiel-Nelson; Javier Sosa; Jose C. Garcia; Roberto Sarmiento; Saeid Nooshabadi

doi:10.1117/12.498585

21 April 2003 High-performance VLSI architecture for video processing

Hector Navarro, Juan A. Montiel-Nelson, Javier Sosa, Jose C. Garcia, Roberto Sarmiento, Saeid Nooshabadi

Proceedings Volume 5117, VLSI Circuits and Systems; (2003) https://doi.org/10.1117/12.498585
Event: Microtechnologies for the New Millennium 2003, 2003, Maspalomas, Gran Canaria, Canary Islands, Spain

Abstract

Real time image processing is a key issue in nowadays multimedia applications. Image filtering and video coding are two basic applications in image processing. Their algorithms are computationally expensive due to both, the number of points of each frame to be processed, and the calculation complexity per point. The VLSI implementation of these algorithms leads to special architectures that are based on systolic arrays, and whose implementation is greedy in silicon area. In this paper, we propose a configurable and bidimensional pipelined VLSI architecture that supports mathematical morphology operations and the block matching algorithm. Remarkable advantages include low power consumption, and a regular and compact design (in terms of core active area) versus the traditional systolic architecture. The architecture is adequate for both morphological image filtering and video compression, depending on the hardware resources of the processing elements. The main advantage of this bidimensional pipeline architecture is the area saving compared with the systolic array implementation. Total area saving was presented in terms of the number of bits of the FIFO memories that can be eliminated. The proposed architecture was verified at high level in C++, at RTL level using Verilog and at C++/RTL level using DEMETER. Required cycle times was measured for a real time morphological filter per dilation/erosion operation, as a function of the incoming resolution. Physical layouts were obtained for the basic slice of the processing element and for the systolic array using the technology of 0,35 microns CMOS from AMS.

Citation Download Citation

Hector Navarro, Juan A. Montiel-Nelson, Javier Sosa, Jose C. Garcia, Roberto Sarmiento, and Saeid Nooshabadi "High-performance VLSI architecture for video processing", Proc. SPIE 5117, VLSI Circuits and Systems, (21 April 2003); https://doi.org/10.1117/12.498585

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