A processor for MPEG decoder SOC: a software/hardware co-design approach

Guojun Yu; Qingdong Yao; Peng Liu; Zhidi Jiang; Fuping Li

doi:10.1117/12.582737

14 March 2005 A processor for MPEG decoder SOC: a software/hardware co-design approach

Guojun Yu, Qingdong Yao, Peng Liu, Zhidi Jiang, Fuping Li

Author Affiliations +

Proceedings Volume 5685, Image and Video Communications and Processing 2005; (2005) https://doi.org/10.1117/12.582737
Event: Electronic Imaging 2005, 2005, San Jose, California, United States

Abstract

Media processing such as real-time compression and decompression of video signal is now expected to be the driving force in the evolution of media processor. In this paper, a hardware and software co-design approach is introduced for a 32-bit media processor: MediaDsp3201 (briefly, MD32), which is realized in 0.18μm TSMC, 200MHz and can achieve 200 million multiply-accumulate (MAC) operations per second. In our design, we have emerged RISC and DSP into one processor (RISC/DSP). Based on the analysis of inherent characteristics of video processing algorithms, media enhancement instructions are adopted into MD32’instruction set. The media extension instructions are physically realized in the processor core, and improves video processing performance effectively with negligible additional hardware cost (2.7%). Considering the high complexity of the operation for media instructions, technology named scalable super pipeline is used to resolve problem of the time delay of pipeline stage (mainly EX stage). Simulation results show that our method can reduce more than 31% and 23% instructions for IDCT compared to MMX and SSE’s implementation and 40% for MC compared to MMX’s implementation.

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Guojun Yu, Qingdong Yao, Peng Liu, Zhidi Jiang, and Fuping Li "A processor for MPEG decoder SOC: a software/hardware co-design approach", Proc. SPIE 5685, Image and Video Communications and Processing 2005, (14 March 2005); https://doi.org/10.1117/12.582737

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