Back end design and implementation of resilient packet ring ASIC

Jishi Li; Fan Zhang; Depeng Jin; Lieguang Zeng

doi:10.1117/12.634027

5 December 2005 Back end design and implementation of resilient packet ring ASIC

Jishi Li, Fan Zhang, Depeng Jin, Lieguang Zeng

Proceedings Volume 6022, Network Architectures, Management, and Applications III; 60222G (2005) https://doi.org/10.1117/12.634027
Event: Asia-Pacific Optical Communications, 2005, Shanghai, China

Abstract

Resilient packet ring (RPR) is a good capacity solution to next generation metropolitan area network (MAN). This paper introduces the back end design of RPR application specific integrated circuit (ASIC) designed independently by Department of Electronic Engineering of Tsinghua University. It draws a back end design flow chart and relates about three key techniques: simultaneous switching output (SSO), design for testability (DFT) and static timing analysis (STA). It makes a brief introduction to each technique. It discusses the ways to avoid SSO problems, to calculate scan chains number, to achieve qualified test pattern fault coverage, and to solve STA violations. In the end, it shows design results and layout figure.

Citation Download Citation

Jishi Li, Fan Zhang, Depeng Jin, and Lieguang Zeng "Back end design and implementation of resilient packet ring ASIC", Proc. SPIE 6022, Network Architectures, Management, and Applications III, 60222G (5 December 2005); https://doi.org/10.1117/12.634027

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