The new bake plate optimized for a PEB process

Shigehiro Goto; Keiji Matsuchika; Akihiro Hisai

doi:10.1117/12.652020

29 March 2006 The new bake plate optimized for a PEB process

Shigehiro Goto, Keiji Matsuchika, Akihiro Hisai

Proceedings Volume 6153, Advances in Resist Technology and Processing XXIII; 61534N (2006) https://doi.org/10.1117/12.652020
Event: SPIE 31st International Symposium on Advanced Lithography, 2006, San Jose, California, United States

Abstract

It is well known that within wafer Critical Dimension (CD) uniformity is especially affected by baking temperature variation during Post Exposure Baking (PEB) process of 193nm photolithography. To develop new baking unit for better CD uniformity, it is important to understand Dynamic Temperature CD Sensitivity (DTCS) of PEB processing at each baking process step. This paper studies the DTCS in the PEB process applying unique experimental procedures. We have added an intentional temperature tilt within wafer at particular processing time during PEB, and we have estimated DTCS from CD and temperature deviation within wafer. Using those scattered data, DTCS curves during PEB process were obtained. The high values of DTCS curve appeared just before the temperature of the wafer reaching the setting temperature of the hot plate. This fact indicates that temperature variation within wafer on this particular step has a large impact on CD uniformity. Therefore, the key to secure highly accurate CD uniformity is to improve temperature controllability within wafer on this processing period in PEB process. Based on these results, we have conducted three optimizations of bake plate for the improvement of the temperature controllability within wafer. CD uniformity was also evaluated with 193nm photoresist.

Citation Download Citation

Shigehiro Goto, Keiji Matsuchika, and Akihiro Hisai "The new bake plate optimized for a PEB process", Proc. SPIE 6153, Advances in Resist Technology and Processing XXIII, 61534N (29 March 2006); https://doi.org/10.1117/12.652020

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