Scatterometry characterization of polysilicon gate profiles in a 90 nm logic process

E. B. Maiken

doi:10.1117/12.724208

5 April 2007 Scatterometry characterization of polysilicon gate profiles in a 90 nm logic process

E. B. Maiken

Author Affiliations +

Proceedings Volume 6518, Metrology, Inspection, and Process Control for Microlithography XXI; 651851 (2007) https://doi.org/10.1117/12.724208
Event: SPIE Advanced Lithography, 2007, San Jose, California, United States

Abstract

Scatterometry was applied in a 90 nm logic process to monitor etched polysilicon gate profiles and establish correlations of inline dimensional measurements to end-of-line electrical test data. Scatterometry data were acquired on test wafers patterned on full-loop production routes, with etched polysilicon profiles intentionally skewed across wide profile ranges, bracketing the nominal 75 nm linewidth target. Scatterometry profiles were benchmarked to cross-section SEM images, and optimal correlations were established across wide process skews to both average top-down SEM linewidths and to end-of-line electrical test data for electrical-CDs and overlap capacitance. Scatterometry measurements were made with commercial Rotating-Compensator Spectroscopic Ellipsometers, with model inversions on four independent spectral components of 0-th order diffracted signals from grating test structures. Profile regression and analysis were based on both real-time parallel computations, and on pre-computed databases. Analyses of linewidth error propagation, correlations, and sensitivities were made using computed databases and measured spectral covariance matrices for the four signal components. Calculations of measurement uncertainties for polysilicon linewidths closely matched cross-tool measurements of 0.1 nm 1-σ site-level precision. At wafer-level, bottom CD mean matching of < 0.1 nm was demonstrated between two production metrology tools in our fab in short-term precision measurements.

Citation Download Citation

E. B. Maiken "Scatterometry characterization of polysilicon gate profiles in a 90 nm logic process", Proc. SPIE 6518, Metrology, Inspection, and Process Control for Microlithography XXI, 651851 (5 April 2007); https://doi.org/10.1117/12.724208

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