Paper
11 June 2007 Characterization and model enablement of high-frequency noise in 90-nm CMOS technology
Zhenrong Jin, Hongmei Li, Susan Sweeney, Radhika Allamraju, David Greenberg, Basanth Jagannanthan, Scott Parker, Xiaowei Tian
Author Affiliations +
Proceedings Volume 6600, Noise and Fluctuations in Circuits, Devices, and Materials; 66001Q (2007) https://doi.org/10.1117/12.724709
Event: SPIE Fourth International Symposium on Fluctuations and Noise, 2007, Florence, Italy
Abstract
A new method based on the lumped-element network representation of the pad-set parasitics is developed to extract the intrinsic drain current noise source and gate resistance from raw measurement data instead of direct de-embedding. The length dependence of BSIM noise model is also corrected using a sub-circuit in the model file. With the new method, we can finally integrate an improved and hardware verified noise model into design kits.
© (2007) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Zhenrong Jin, Hongmei Li, Susan Sweeney, Radhika Allamraju, David Greenberg, Basanth Jagannanthan, Scott Parker, and Xiaowei Tian "Characterization and model enablement of high-frequency noise in 90-nm CMOS technology", Proc. SPIE 6600, Noise and Fluctuations in Circuits, Devices, and Materials, 66001Q (11 June 2007); https://doi.org/10.1117/12.724709
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KEYWORDS
Transistors

Data modeling

Resistance

CMOS technology

Field effect transistors

Instrument modeling

Radon

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