Study of nanoimprint lithography for applications toward 22nm node CMOS devices

Ikuo Yoneda; Shinji Mikami; Takumi Ota; Takeshi Koshiba; Masamitsu Ito; Tetsuro Nakasugi; Tatsuhiko Higashiki

doi:10.1117/12.771149

14 March 2008 Study of nanoimprint lithography for applications toward 22nm node CMOS devices

Ikuo Yoneda, Shinji Mikami, Takumi Ota, Takeshi Koshiba, Masamitsu Ito, Tetsuro Nakasugi, Tatsuhiko Higashiki

Proceedings Volume 6921, Emerging Lithographic Technologies XII; 692104 (2008) https://doi.org/10.1117/12.771149
Event: SPIE Advanced Lithography, 2008, San Jose, California, United States

Abstract

Nanoimprint lithography is one of the candidates for NGL. Recently, the "S-FIL TM" (Step and Flash Imprint Lithography) has been developed by MII (Molecular Imprints, Inc.). Accordingly, it is necessary to build next-generation devices and study unit processes without delay. Because of good resolution, CD uniformity and LER, nanoimprint lithography is attractive. However, nanoimprint lithography (S-FIL) involves risks. In order to judge whether the S-FIL is applicable to the study of unit processes and test device fabrication, we had studied the feasibility of S-FIL technology. As a result of previous work, we obtained the results of basic evaluation and confirmed the applicability of nanoimprint lithography for unit process study and basic test device fabrication. However, application of nanoimprint lithography to various test devices requires the template resolution of 22nmHP, OL accuracy on multilayer resist, and defect density for various patterns. Therefore, in order to judge whether the S-FIL application is extendable to various test devices, we studied the characteristics of S-FIL. As a result of this work, we confirmed that the nanoimprint application is extendable to fabrication of various test devices. And as a result of basic evaluation, improvement of template resolution is confirmed and the value of 22nmHP is obtained. We confirmed the robustness of the alignment process. The defect density is related in pattern density and spread time. Thus, reduced DD without throughput loss is required.

Citation Download Citation

Ikuo Yoneda, Shinji Mikami, Takumi Ota, Takeshi Koshiba, Masamitsu Ito, Tetsuro Nakasugi, and Tatsuhiko Higashiki "Study of nanoimprint lithography for applications toward 22nm node CMOS devices", Proc. SPIE 6921, Emerging Lithographic Technologies XII, 692104 (14 March 2008); https://doi.org/10.1117/12.771149

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