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Double patterning (DP) is the first candidate for extension of ArF immersion lithography, and topcoat-less (TC-less)
process is an attractive process candidate compared to a topcoat process because it can make DP process simpler and
reduce the chip manufacturing cost. To make the DP process viable, TC-less process performance including defectivity,
auto focus (AF) and overlay performance must be validated. Nikon's latest volume production immersion lithography
tool (S620D), was used for TC-less process evaluation. While S620D shows good defectivity results with both topcoat
and TC-less process at 700mm/s scan speed, TC-less process showed slight improvement in defectivity compared to
topcoat process. One reason being that TC-less process can suppress topcoat originated defect such as topcoat blister.
The second reason is that TC-less resist can attain higher hydrophobicity than topcoat. Higher hydrophobicity is
advantageous for high speed scanning because of stable movement of water meniscus, resulting in better defectivity
performance. Defectivity results showed clear correlation to dynamic receding contact angle (D-RCA).
Blob defect reduction is one of the challenges with TC-less resist process, because hydrophobic surface repels rinse
water applied during development rinse process hence generating blob defect. However, the recent material
improvements of TC-less resist have overcome this challenge and showed excellent blob defect performance. The
hydrophobicity control during development process is the key factor in defect reduction.
Wafer edge process is also very important for immersion lithography. The preferable wafer edge treatment for both TCless
and topcoat process is to maintain uniform hydrophobicity over the entire wafer including wafer edge. While topcoat
can be removed perfectly by development, unexposed TC-less resist remains on the wafer edge. WEE (wafer edge
exposure) process can remove the excess resist after exposure, it's effectiveness was confirmed through experimental
results.
AF and overlay repeatability was evaluated on both topcoat and TC-less process; similar and sufficient performance was
obtained on both processes. Based on cost of ownership calculations it is believed a 30% material cost and 10% track
hardware cost reduction is feasible.
These evaluations provide convincing evidence that TC-less process is ready for 32nm generation and beyond.
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