Using a highly accurate self-stop Cu-CMP model in the design flow

Kyoko Izuha; Takashi Sakairi; Shunichi Shibuki; Monalisa Bora; Osama Hatem; Ruben Ghulghazaryan; Norbert Strecker; Jeff Wilson; Noritsugu Takeshita

doi:10.1117/12.845653

2 April 2010 Using a highly accurate self-stop Cu-CMP model in the design flow

Kyoko Izuha, Takashi Sakairi, Shunichi Shibuki, Monalisa Bora, Osama Hatem, Ruben Ghulghazaryan, Norbert Strecker, Jeff Wilson, Noritsugu Takeshita

Author Affiliations +

Proceedings Volume 7641, Design for Manufacturability through Design-Process Integration IV; 76410V (2010) https://doi.org/10.1117/12.845653
Event: SPIE Advanced Lithography, 2010, San Jose, California, United States

Abstract

An accurate model for the self-stop copper chemical mechanical polishing (Cu-CMP) process has been developed using CMP modeling technology from Mentor Graphics. This technology was applied on data from Sony to create and optimize copper electroplating (ECD), Cu-CMP, and barrier metal polishing (BM-CMP) process models. These models take into account layout pattern dependency, long range diffusion and planarization effects, as well as microloading from local pattern density. The developed ECD model accurately predicted erosion and dishing over the entire range of width and space combinations present on the test chip. Then, the results of the ECD model were used as an initial structure to model the Cu-CMP step. Subsequently, the result of Cu-CMP was used for the BM-CMP model creation. The created model was successful in reproducing the measured data, including trends for a broad range of metal width and densities. Its robustness is demonstrated by the fact that it gives acceptable prediction of final copper thickness data although the calibration data included noise from line scan measurements. Accuracy of the Cu-CMP model has a great impact on the prediction results for BM-CMP. This is a critical feature for the modeling of high precision CMP such as self-stop Cu-CMP. Finally, the developed model could successfully extract planarity hotspots that helped identify potential problems in production chips before they were manufactured. The output thickness values of metal and dielectric can be used to drive layout enhancement tools and improve the accuracy of timing analysis.

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Kyoko Izuha, Takashi Sakairi, Shunichi Shibuki, Monalisa Bora, Osama Hatem, Ruben Ghulghazaryan, Norbert Strecker, Jeff Wilson, and Noritsugu Takeshita "Using a highly accurate self-stop Cu-CMP model in the design flow", Proc. SPIE 7641, Design for Manufacturability through Design-Process Integration IV, 76410V (2 April 2010); https://doi.org/10.1117/12.845653

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