High throughput VLSI architecture for multiresolution integer motion estimation in high definition AVS video encoder

HaiBing Yin; Honggang Qi; Hao Xu; Xiaodong Xie; Wen Gao

doi:10.1117/12.863475

4 August 2010 High throughput VLSI architecture for multiresolution integer motion estimation in high definition AVS video encoder

HaiBing Yin, Honggang Qi, Hao Xu, Xiaodong Xie, Wen Gao

Author Affiliations +

Proceedings Volume 7744, Visual Communications and Image Processing 2010; 77441W (2010) https://doi.org/10.1117/12.863475
Event: Visual Communications and Image Processing 2010, 2010, Huangshan, China

Abstract

This paper proposes a hardware friendly multi-resolution motion estimation algorithm and VLSI architecture for high definition MPEG-like video encoder hardware implementation. By parallel searching and utilizing the high correlation in multi-resolution reference pixels, huge throughput and computation due to large search window are alleviated considerably. Sixteen way parallel processing element arrays with configurable multiplying technologies achieve fast search with regular data access and efficient data reuse. Also, the parallel arrays can be efficiently reused at three hierarchical levels for sequential motion vector refinement. The modified algorithm reaches a good balance between implementation complexity and search performance. Also, the logic circuit and on-chip SRAM consumption of the VLSI architecture are moderate.

Citation Download Citation

HaiBing Yin, Honggang Qi, Hao Xu, Xiaodong Xie, and Wen Gao "High throughput VLSI architecture for multiresolution integer motion estimation in high definition AVS video encoder", Proc. SPIE 7744, Visual Communications and Image Processing 2010, 77441W (4 August 2010); https://doi.org/10.1117/12.863475

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