FPGA design of a real-time edge enhancing smoothing filter

Nimit Pandya; Chang Choo

doi:10.1117/12.2008538

19 February 2013 FPGA design of a real-time edge enhancing smoothing filter

Nimit Pandya, Chang Choo

Proceedings Volume 8656, Real-Time Image and Video Processing 2013; 865607 (2013) https://doi.org/10.1117/12.2008538
Event: IS&T/SPIE Electronic Imaging, 2013, Burlingame, California, United States

Abstract

Traditional noise removal filters have an undesirable side effect of blurring edges, which is unacceptable for some image processing applications. To overcome this problem, our ongoing project evaluates an edge enhancing smoothening filter and implements it on FPGAs to reduce noise while sharpening edges. One such edge enhancing smoothing filter consists of a combination of the bilateral filter (used for edge preserving smoothing) and the Shock filter (used for edge enhancement) to achieve the desired result. This paper describes an implementation of the bilateral filter on Altera FPGAs. Shock filter part is then briefly described. Area and speed performance results for different Altera FPGA families are comparatively shown.

Citation Download Citation

Nimit Pandya and Chang Choo "FPGA design of a real-time edge enhancing smoothing filter", Proc. SPIE 8656, Real-Time Image and Video Processing 2013, 865607 (19 February 2013); https://doi.org/10.1117/12.2008538

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