In-field in-design metrology target integration for advanced CD and overlay process control via DoseMapper and high order overlay correction for 28nm and beyond logic node

J. Ducoté; F. Bernard-Granger; B. Le-Gratiet; R. Bouyssou; R. Bianchini; J. C. Marin; M. P. Baron; F. Gardet; T. Devoivre; E. Batail; C. Pouly; D. Gueze; L. Thevenon

doi:10.1117/12.2010909

10 April 2013 In-field in-design metrology target integration for advanced CD and overlay process control via DoseMapper and high order overlay correction for 28nm and beyond logic node

J. Ducoté, F. Bernard-Granger, B. Le-Gratiet, R. Bouyssou, R. Bianchini, J. C. Marin, M. P. Baron, F. Gardet, T. Devoivre, E. Batail, C. Pouly, D. Gueze, L. Thevenon

Author Affiliations +

Proceedings Volume 8681, Metrology, Inspection, and Process Control for Microlithography XXVII; 868136 (2013) https://doi.org/10.1117/12.2010909
Event: SPIE Advanced Lithography, 2013, San Jose, California, United States

Abstract

Current process tool performances are getting significantly enhanced by the adoption of advanced process correction application such as DoseMapper for CD or high order overlay correction for overlay. These process control capabilities need appropriate sampling to be efficient. Usually for in field metrology sampling we used to operate with metrology targets placed inside the scribe lines, however in this case the larger the chip the less scribe lines we have and the less relevant is the intrafield sampling. As ST is an IDM we have the opportunity to share with our design division this process control problematic. Since 45/40nm node we have started to put in place the so-called EMET (Embedded Metrology Target) strategy which consists in in-design metrology targets placement. Initially these targets were placed using tiling tools but it soon appeared to be not efficient and even impossible when we talk about targets involving complex metal stack. This papers talks about our current embedded metrology target strategy which has been adapted to enable appropriate target placement for CD and overlay for all critical layers from active to via/metal’s. Solutions needed to be put in place to (i) keep the circuit safe by using Design Rule clean metrology targets, (ii) be highly visible by the designers by placing targets at chip floor planning definition (iii) be upgradable by enabling target re-designs without impact on chip design version.

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J. Ducoté, F. Bernard-Granger, B. Le-Gratiet, R. Bouyssou, R. Bianchini, J. C. Marin, M. P. Baron, F. Gardet, T. Devoivre, E. Batail, C. Pouly, D. Gueze, and L. Thevenon "In-field in-design metrology target integration for advanced CD and overlay process control via DoseMapper and high order overlay correction for 28nm and beyond logic node", Proc. SPIE 8681, Metrology, Inspection, and Process Control for Microlithography XXVII, 868136 (10 April 2013); https://doi.org/10.1117/12.2010909

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