Optimization of a PCRAM Chip for high-speed read and highly reliable reset operations

Xiaoyun Li; Houpeng Chen; Xi Li; Qian Wang; Xi Fan; Jiajun Hu; Yu Lei; Qi Zhang; Zhen Tian; Zhitang Song

doi:10.1117/12.2245306

12 October 2016 Optimization of a PCRAM Chip for high-speed read and highly reliable reset operations

Xiaoyun Li, Houpeng Chen, Xi Li, Qian Wang, Xi Fan, Jiajun Hu, Yu Lei, Qi Zhang, Zhen Tian, Zhitang Song

Proceedings Volume 9818, 2016 International Workshop on Information Data Storage and Tenth International Symposium on Optical Storage; 98180L (2016) https://doi.org/10.1117/12.2245306
Event: 2016 International Workshop on Information Data Storage and Tenth International Symposium on Optical Storage, 2016, Changzhou, China

Abstract

The widely used traditional Flash memory suffers from its performance limits such as its serious crosstalk problems, and increasing complexity of floating gate scaling. Phase change random access memory (PCRAM) becomes one of the most potential nonvolatile memories among the new memory techniques. In this paper, a 1M-bit PCRAM chip is designed based on the SMIC 40nm CMOS technology. Focusing on the read and write performance, two new circuits with high-speed read operation and highly reliable reset operation are proposed. The high-speed read circuit effectively reduces the reading time from 74ns to 40ns. The double-mode reset circuit improves the chip yield. This 1M-bit PCRAM chip has been simulated on cadence. After layout design is completed, the chip will be taped out for post-test.

Citation Download Citation

Xiaoyun Li, Houpeng Chen, Xi Li, Qian Wang, Xi Fan, Jiajun Hu, Yu Lei, Qi Zhang, Zhen Tian, and Zhitang Song "Optimization of a PCRAM Chip for high-speed read and highly reliable reset operations", Proc. SPIE 9818, 2016 International Workshop on Information Data Storage and Tenth International Symposium on Optical Storage, 98180L (12 October 2016); https://doi.org/10.1117/12.2245306

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