Optimization of J-V characteristic in diode array for phase change memory

Heng Wang; Yan Liu; Bo Liu; Chao Zhang; Zhitang Song

doi:10.1117/12.2246915

12 October 2016 Optimization of J-V characteristic in diode array for phase change memory

Heng Wang, Yan Liu, Bo Liu, Chao Zhang, Zhitang Song

Proceedings Volume 9818, 2016 International Workshop on Information Data Storage and Tenth International Symposium on Optical Storage; 98180R (2016) https://doi.org/10.1117/12.2246915
Event: 2016 International Workshop on Information Data Storage and Tenth International Symposium on Optical Storage, 2016, Changzhou, China

Abstract

In this paper, current density-voltage (J-V) characteristic of dual trench diode array have been investigated by both TCAD model and experimental method. It is shown that the arsenic concentration in buried N+ layer (BNL), epitaxial (EPI) layer thickness, and the dosage of P region in PN junction are expected to be the prominent factors responsible for both of the leakage and drive current performance according to TCAD simulation. By introducing the optimal siliconbased results, the 4×4 diode arrays were successfully manufactured by 40nm CMOS technology. The median values of drive and reverse leakage current densities are ~7.30×10^-2 A/μm² and 5.61×10^-9 A/μm², respectively. The breakdown voltages (BVDs) of diode array are exceeding 6V, and the J_on/J_off ratios of ~10⁹, which can satisfy the requirements of phase change memory (PCM) applications.

Citation Download Citation

Heng Wang, Yan Liu, Bo Liu, Chao Zhang, and Zhitang Song "Optimization of J-V characteristic in diode array for phase change memory", Proc. SPIE 9818, 2016 International Workshop on Information Data Storage and Tenth International Symposium on Optical Storage, 98180R (12 October 2016); https://doi.org/10.1117/12.2246915

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